View UPD75P4308_98735.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P4308
4-BIT SINGLE-CHIP MICROCONTROLLER
The PD75P4308 replaces the PD754304's internal mask ROM with a one-time PROM and features expanded ROM capacity. Because the PD75P4308 supports programming by users, it is suitable for use in prototype testing for system development using the PD754302 and 754304 products, and for use in small-lot production. Detailed descriptions of functions are provided in the following document. Be sure to read the document before designing.
PD754304 User's Manual: U10123E
FEATURES
* Compatible with PD754304 * Memory capacity: * PROM : 8192 x 8 bits * RAM : 256 x 4 bits * Can operate in the same power supply voltage as the mask version PD754304 * VDD = 1.8 to 5.5 V * Adopts a compact shrink SOP package
ORDERING INFORMATION
Part Number Package 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
PD75P4308GS
Caution On-chip pull-up resistors by mask option are not provided.
The information in this document is subject to change without notice.
Document No. U10909EJ2V0DS00 (2nd edition) Date Published January 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1996
PD75P4308
OVERVIEW OF FUNCTIONS
Item Instruction execution time Function * 0.95, 1.91, 3.81, or 15.3 s (system clock: @ 4.19 MHz) * 0.67, 1.33, 2.67, or 10.7 s (system clock: @ 6.0 MHz) 8192 x 8 bits 256 x 4 bits * 4-bit manipulation: 8 registers x 4 banks * 8-bit manipulation: 4 registers x 8 banks 8 18 4 30 3 channels * 8-bit timer/event counter: 2 channels (Can be used as a 16-bit timer/event counter) * 8-bit basic interval timer/watchdog timer: 1 channel * 3-wire serial I/O mode ... MSB/LSB-first switchable * 2-wire serial I/O mode 16 bits * , 524, 262, 65.5 kHz (system clock: @ 4.19 MHz) * , 750, 375, 93.8 kHz (system clock: @ 6.0 MHz) Vectored interrupts Test input System clock oscillator Standby functions Operating ambient temperature Power supply voltage Package External: 3, Internal: 4 External: 1 Ceramic/crystal oscillator STOP mode/HALT mode TA = -40 to +85C VDD = 1.8 to 5.5 V 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Connection of on-chip pull-up resistors can be specified by software: 7 Connection of on-chip pull-up resistors can be specified by software: 18 13-V withstand voltage
Internal memory
PROM RAM
General-purpose register
I/O ports
CMOS input CMOS I/O N-ch open-drain I/O Total
Timers
Serial interface
Bit sequential buffer Clock output (PCL)
2
PD75P4308
CONTENTS
1. PIN CONFIGURATION (Top View) .................................................................................................... 4 2. BLOCK DIAGRAM .............................................................................................................................. 5 3. PIN FUNCTIONS ................................................................................................................................. 6
3.1 3.2 3.3 3.4 Port Pins ........................................................................................................................................................ 6 Non-port Pins ................................................................................................................................................ 8 Pin I/O Circuits .............................................................................................................................................. 9 Recommended Connection of Unused Pins ............................................................................................ 11
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ......................................... 12
4.1 Differences between Mk I Mode and Mk II Mode ..................................................................................... 12 4.2 Setting of Stack Bank Selection (SBS) Register ..................................................................................... 13
5. DIFFERENCES BETWEEN PD75P4308 AND PD754302, 754304 .......................................... 14 6. MEMORY CONFIGURATION ............................................................................................................ 15 7. INSTRUCTION SET .......................................................................................................................... 17 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ............................................... 28
8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................... Program Memory Write Procedure ........................................................................................................... Program Memory Read Procedure ........................................................................................................... One-Time PROM Screening ....................................................................................................................... 28 29 30 31
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 32 10. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ............................................................ 45 11. PACKAGE DRAWINGS ..................................................................................................................... 47 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 48 APPENDIX A. COMPARISON OF PD750004, 754304, AND 75P4308 FUNCTIONS ..................... 49 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 51 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 55
3
PD75P4308
1. PIN CONFIGURATION (Top View)
* 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
PD75P4308GS
Vss X1 X2 RESET P33/MD3 P32/MD2 P31/MD1 P30/MD0 P81 P80 P23 P22/PCL P21/PTO1 P20/PTO0 P03/SI P02/SO/SB0 P01/SCK P00/INT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P50/D4 P51/D5 P52/D6 P53/D7 P60/KR0/D0 P61/KR1/D1 P62/KR2/D2 P63/KR3/D3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P13/TI0/TI1 P12/INT2 P11/INT1 P10/INT0 VDD VPP Note
Note Connect VPP directly to VDD during normal operations.
PIN IDENTIFICATIONS
P00 to P03 P10 to P13 P20 to P23 P30 to P33 P50 to P53 P60 to P63 P70 to P73 P80, P81 KR0 to KR7 VDD VSS VPP SCK : Port0 : Port1 : Port2 : Port3 : Port5 : Port6 : Port7 : Port8 : Key Return 0 to 7 : Positive Power Supply : GND : Programming Power Supply : Serial Clock SI SO SB0 RESET TI0, 1 PTO0, 1 PCL INT0, 1, 4 INT2 X1, 2 MD0 to 3 D0 to D7 : Serial Input : Serial Output : Serial Bus 0 : Reset : Timer Input 0, 1 : Programmable Timer Output 0, 1 : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : System Clock Oscillation 1, 2 : Mode Selection 0 to 3 : Data Bus 0 to 7
4
PD75P4308
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER/ WATCHDOG TIMER
BIT SEQ. BUFFER (16) 4 PORT0 PROGRAM COUNTER ALU SP (8) CY SBS BANK 4 PORT2 4 P20-P23 P30/MD0P33/MD3 P50/D4P53/D7 P60/KR0/D0P63/KR3/D3 P70-P73 4 PORT1 4 P10-P13 4 P00-P03
INTBT TOUT0 TI0/TI1/P13 PTO0/P20 PTO1/P21
8-BIT TIMER/EVENT COUNTER#0 8-BIT TIMER/EVENT COUNTER#1
INTT0
CASCADED 16-BIT TIMER/ EVENT COUNTER
INTT1 SI/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60/D0- 8 KR3/P63/D3 KR4/P70KR7/P73 PROM PROGRAM MEMORY 8192 x 8 BITS GENERAL REG. DECODE AND CONTROL
4
PORT3
4
4 RAM DATA MEMORY 256 x 4 BITS
PORT5
4
4
PORT6
4
INTERRUPT CONTROL fx/2 N CLOCK CLOCK OUTPUT CONTROL DIVIDER PCL/P22 CPU CLOCK CLOCK GENERATOR X1 X2 STAND BY CONTROL
4
PORT7
4
2
PORT8
2
P80, P81
VPP VDD Vss RESET
5
PD75P4308
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Alternate function INT4 SCK SO/SB0 SI INT0 INT1 INT2 TI0/TI1 I/O PTO0 PTO1 PCL -- I/O MD0 MD1 MD2 MD3 I/O D4 D5 D6 D7 Programmable 4-bit I/O port (PORT3). Input and output can be specified in singlebit units. Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. N-ch open-drain 4-bit input/output port (PORT5). 13-V withstand during open-drain. Data input/output pin for program memory (PROM) write/verify (upper 4 bits). No Input E-B 4-bit input port (PORT1). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. Noise elimination circuit can be selected only for P10/INT0. 4-bit I/O port (PORT2). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. No Input 8-bit I/O No After reset Input I/O Circuit typeNote 1 -A -B -C -C
Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P50Note 2 P51Note 2 P52Note 2 P53Note 2
I/O Input I/O I/O Input Input
Function 4-bit input port (PORT0). For P01 to P03, connections of on-chip pullup resistors are software-specificable in 3bit units.
No
Input
E-B
No
Highimpedance
M-E
Notes 1. Circuit types in brackets indicate Schmitt trigger input. 2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.
6
PD75P4308
3.1 Port Pins (2/2)
Alternate function KR0/D0 KR1/D1 KR2/D2 KR3/D3 I/O KR4 KR5 KR6 KR7 I/O -- -- 2-bit I/O port (PORT8). Connections of on-chip pull-up resistors are software-specifiable in 2-bit units. No Input E-B 8-bit I/O Yes After reset Input I/O Circuit typeNote -A
Pin name P60 P61 P62 P63 P70 P71 P72 P73 P80 P81
I/O I/O
Function Programmable 4-bit I/O port (PORT6). Input and output can be specified in single-bit units. Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. Data input/output pin for program memory (PROM) write/verify (lower 4 bits). 4-bit I/O port (PORT7). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units.
Input
-A
Note Circuit types in brackets indicate the Schmitt trigger input.
7
PD75P4308
3.2 Non-port Pins
Alternate function P13 P20 P21 P22 I/O P01 P02 Clock output Serial clock I/O Serial data output Serial data bus I/O Serial data input Edge-triggered vectored interrupt input (triggered by both rising and falling edges). Edge-triggered vectored interrupt input (detected edge is selectable). Noise elimination circuit selectable in INT0/P10. INT1 INT2 KR0 to KR3 Input P11 P12 P60/D0 to P63/D3 P70 to P73 Input -- Input Input -- P30 to P33 -- Ceramic/crystal connection for system clock oscillation. If using an external clock, input it to X1 and input the inverted clock to X2. System reset input Mode selection for program memory (PROM) write/ verify. Data bus pin for program memory (PROM) write/verify. -- -- Rising edge-triggered test input Falling edge-triggered testable input Noise elimination circuit appended/ asynchronous selectable Asynchronous Asynchronous Input -A -- Input -A -B After reset Input Input I/O Circuit typeNote 1 -C E-B
Pin name TI0/TI1 PTO0 PTO1 PCL SCK SO/SB0
I/O Input Output
Function External event pulse input to timer/event counter Timer/event counter output
SI INT4
Input
P03 P00
-C
INT0
Input
P10
--
-C
KR4 to KR7 X1 X2 RESET MD0 to MD3
-- Input
E-B
D0 to D3
I/O
P60/KR0 to P63/KR3 P50 to P53
Input
-A
D4 to D7 VPPNote 2 --
M-E Program supply voltage in program memory (PROM) write/verify mode. In normal operation mode, connect directly to VDD. Apply +12.5 V in PROM write/verify mode. -- --
--
VDD VSS
-- --
-- --
Positive power supply Ground
-- --
-- --
Notes 1. Circuit types in brackets indicate Schmitt trigger input. 2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin.
8
PD75P4308
3.3 Pin I/O Circuits The equivalent circuits for the PD75P4308's pin are shown in simplified schematic diagrams below. (1/2)
TYPE A TYPE D VDD VDD Data P-ch IN Output disable N-ch P-ch OUT
N-ch
CMOS standard input buffer TYPE B
Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch
IN
Data Type D Output disable
IN/OUT
Schmitt trigger input with hysteresis characteristics.
Type A
P.U.R.: Pull-Up Resistor
TYPE B-C VDD P.U.R. P.U.R. enable
TYPE F-A VDD P.U.R. P.U.R. enable Data IN Type D Output disable P-ch
P-ch
IN/OUT
P.U.R. : Pull-Up Resistor Schmitt trigger input with hysteresis characteristics.
Type B
P.U.R.: Pull-Up Resistor
9
PD75P4308
(2/2)
TYPE F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) Note P.U.R.: Pull-Up Resistor N-ch VDD P-ch IN/OUT P.U.R.Note Voltage limitation (+13 V circuit withstand voltage) Pull-up resistor that operates only when an input instruction has been executed (current flows from VDD to the pin when the pin is low). Input instruction P-ch data output disable VDD P-ch N-ch (+13 V withstand voltage) TYPE M-E IN/OUT
10
PD75P4308
3.4 Recommended Connection of Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI P10/INT0 to P12/INT2 P13/TI0/TI1 P20/PTO0 P21/PTO1 P22/PCL P23 P30/MD0 to P33/MD3 P50 to P53 P60/KR0 to P63/KR3 P70/KR4 to P73/KR7 P80, P81 VPP Connect to VSS. Input mode : connect individually to VSS or VDD via a resistor. Output mode: open Be sure to connect directly to VDD. Input mode : connect individually to VSS or VDD via a resistor. Output mode: open Connecto to VSS. Connect to VSS or VDD. Recommended connection Connect to VSS or VDD. Connect individually to VSS or VDD via a resistor.
11
PD75P4308
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
Setting a stack bank selection (SBS) register for the PD75P4308 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the PD754302 or 754304 using the PD75P4308. When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of PD754302 and 754304) When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of PD754302 and 754304) 4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the PD75P4308. Table 4-1. Differences between Mk I Mode and Mk II Mode
Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank Stack bytes Instruction BRA !addr1 CALLA !addr1 CALL !addr PC12-0 8192 256 x 4 Memory bank 0 2 bytes Not provided 3 bytes Provided Mk I Mode Mk II Mode
Instruction
3 machine cycles 2 machine cycles Mk I mode of PD754302 and 754304
4 machine cycles 3 machine cycles Mk II mode of PD754302 and 754304
execution time CALLF !faddr Supported mask ROM versions
Caution The Mk II mode supports 16 Kbytes or more of program area in the 75X and 75XL Series. This mode allows the software compatibility with 16-Kbyte or more versions to be improved. Compared with the Mk I mode, selecting the Mk II mode increases the stack bytes by one during execution of the subroutine call instruction. When a CALL !addr or CALLF !faddr instruction is used, the instruction execution time increases by one machine cycle. Therefore, if RAM efficiency or throughput is more important than software compatibility, use the Mk I mode.
12
PD75P4308
4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 1000B at the beginning of the program. When using the Mk II mode, be sure to initialize it to 0000B. Figure 4-1. Format of Stack Bank Selection Register
Address F84H 3 SBS3 2 SBS2 1 SBS1 0 SBS0 Symbol SBS
Stack area specification
0 0 Memory bank 0
Setting prohibited other than above
0
Be sure to enter "0" for bit 2.
Mode selection specification
0 1 Mk II mode Mk I mode
Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in the Mk I mode. When using instructions for the Mk II mode, set SBS3 to "0" to enter the Mk II mode before using the instructions. 2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register.
13
PD75P4308
5. DIFFERENCES BETWEEN PD75P4308 AND PD754302, 754304
The PD75P4308 replaces the internal mask ROM in the PD754302 and 754304 with a one-time PROM and features expanded ROM capacity. The PD75P4308's Mk I mode supports the Mk I mode in the PD754302 and 754304 and the PD75P4308's Mk II mode supports the Mk II mode in the PD754302 and 754304. Table 5-1 lists differences among the PD75P4308 and the PD754302 and 754304. Be sure to check the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production. For details of CPU functions and incorporated hardware, refer to PD754304 User's Manual (U10123E). Table 5-1. Differences between PD75P4308 and PD754302, 754304
Item Program counter Program memory (bytes) 11-bit Mask ROM 2048 Data memory (x 4 bits) Mask options Pull-up resistor for PORT5 Wait time in RESET state Pin configuration Pins 5 to 8 Pin 19 Pins 29 to 32 P33-P30 IC P63/KR3-P60/KR0 P33/MD3-P30/MD0 VPP P63/KR3/D3P60/KR0/D0 P53/D7-P50/D4 Yes (Selectable from 217/fX and 215/fX)Note No (fixed at 215/fX)Note 256 Yes (On-chip/not on-chip specifiable) No (On-chip not possible)
PD754302
12-bit
PD754304
13-bit
PD75P4308
Mask ROM 4096
One-time PROM 8192
Pins 33 to 36 Other
P53-P50
Noise resistance and noise radiation may differ due to the different circuit complexities and mask layouts.
Note 217/fX: 21.8 ms @6.0-MHz operation, 31.3 ms @4.19-MHz operation. 215/fX: 5.46 ms @6.0-MHz operation, 7.81 ms @4.19-MHz operation. Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS (not ES) of the mask ROM version.
14
PD75P4308
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
7 0000H
6
5 0
0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits)
MBE RBE
0002H
MBE RBE
0
INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction entry address
0004H
MBE RBE
0
INT0 start address (upper 5 bits) INT0 start address (lower 8 bits)
0006H
MBE RBE
0
INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) BRCB !caddr instruction branch address
0008H
MBE RBE
0
INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits)
000AH
MBE RBE
0
INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits)
000CH MBE RBE
0
INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits)
Branch address for the following instructions * BR BCDE * BR BCXA * BR !addr * CALL !addr * BRA !addr1Note * CALLA !addr1 Note Branch/call address by GETI BR $addr instruction relative branch address (-15 to -1, +2 to +16)
0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH
BRCB !caddr instruction branch address
Note Can be used only in the Mk II mode. Remark For instructions other than those noted above, the "BR PCDE" and "BR PCXA" instructions can be used to branch to addresses with changes in the PC's lower 8 bits only.
15
PD75P4308
Figure 6-2. Data Memory Map
Data memory General register area 000H (32 x 4) 01FH 020H Data area static RAM (256 x 4)
Memory bank
Stack area 256 x 4 (224 x 4)
0
0FFH
Not incorporated
F80H 128 x 4
Peripheral hardware area FFFH
15
16
PD75P4308
7. INSTRUCTION SET
(1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, refer to RA75X Assembler Package User's Manual Language (EEU-1363)). When there are several codes, select and use just one. Uppercase letters, and + and - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for details, refer to PD754304 User's Manual (U10123E)). Labels that can be entered for fmem and pmem are restricted.
Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-1FFFH immediate data or label 0000H-1FFFH immediate data or label (in Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (however, bit0 = 0) or label PORT0-PORT3, PORT5-PORT8 IEBT, IECSI, IET0, IET1, IE0-IE2, IE4 RB0-RB3 MB0, MB15 Coding format
Note When processing 8-bit data, only even addresses can be specified.
17
PD75P4308
(2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IExxx RBS MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority select register : Interrupt enable flag : Register bank select register : Memory bank select register : Processor clock control register : Delimiter for address and bit : Contents of address xx : Hexadecimal data
PORTn : Port n (n = 0 to 3, 5 to 8)
18
PD75P4308
(3) Description of symbols used in addressing area
*1
MB = MBE*MBS (MBS = 0, 15) MB = 0 MBE = 0 MBE = 1 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) : MB = MBS (MBS = 0, 15) Data memory addressing
*2 *3
*4 *5 *6 *7
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr, addr1 = 0000H-1FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 (Current PC) +2 to (Current PC) +16
*8
caddr = 0000H-0FFFH (PC12 = 0) or 1000H-1FFFH (PC12 = 1)
Program memory addressing
*9 *10 *11
faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-1FFFH (Mk II mode only)
Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas.
19
PD75P4308
(4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip ******************************************************************************** S = 0 * Skipped instruction is 1-byte or 2-byte instruction ************ S = 1 * Skipped instruction is 3-byte instructionNote *********************** S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times.
20
PD75P4308
No. of Machine bytes cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg1 XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC12 - 8 + DE)ROM XA (PC12 - 8 + XA)ROM XA (BCDE)ROMNote XA (BCXA)ROMNote *6 *6 *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String-effect A String-effect B Addressing Skip condition area String-effect A
Group Transfer
Mnemonic MOV
Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA
Operation
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
Table reference
MOVT
XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA
Note As for the B register, only the lower 1 bit is valid.
21
PD75P4308
No. of Machine bytes cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 Addressing Skip condition area *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
Group Bit transfer
Mnemonic MOV1
Operand CY, fmem.bit CY, pmem.@L CY, @H + mem.bit fmem.bit, CY pmem.@L, CY @H + mem.bit, CY
Operation CY (fmem.bit) CY (pmem7 - 2 + L3 - 2.bit (L1 - 0)) CY (H + mem3 - 0.bit) (fmem.bit) CY (pmem7 - 2 + L3 - 2.bit (L1 - 0)) CY (H + mem3 - 0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A, CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY A A ^ n4 A A ^ (HL) XA XA ^ rp' rp'1 rp'1 ^ XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA
Operation
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
*1
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
AND
A, #n4 A, @HL XA, rp' rp'1, XA
*1
OR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
22
PD75P4308
No. of Machine bytes cycle 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 Addressing Skip condition area
Group Accumulator manipulate Increment/ decrement
Mnemonic RORC NOT INCS A A
Operand
Operation CY A0, A3 CY, An - 1 An AA reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg =n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY
reg rp1 @HL mem
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
DECS
reg rp'
Compare
SKE
reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
Carry flag manipulate
SET1 CLR1 SKT NOT1
CY CY CY CY
CY = 1
23
PD75P4308
No. of Machine bytes cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Addressing Skip condition area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L) = 1 (@H + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H + mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1
Group Memory bit manipulate
Mnemonic SET1
Operand mem.bit fmem.bit pmem.@L @H + mem.bit
Operation (mem.bit) 1 (fmem.bit) 1 (pmem7 - 2 + L3 - 2.bit(L1 - 0)) 1 (H+mem3 - 0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7 - 2 + L3 - 2.bit(L1 - 0)) 0 (H+mem3 - 0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7 - 2 + L3 - 2.bit(L1 - 0)) = 1 Skip if (H + mem3 - 0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7 - 2 + L3 - 2.bit(L1 - 0)) = 0 Skip if (H + mem3 - 0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7 - 2 + L3 - 2.bit (L1 - 0)) = 1 and clear Skip if (H + mem3 - 0.bit) = 1 and clear CY CY ^ (fmem.bit) CY CY ^ (pmem7 - 2 + L3 - 2.bit(L1 - 0)) CY CY ^ (H + mem3 - 0.bit) CY CY v (fmem.bit) CY CY v (pmem7 - 2 + L3 - 2.bit(L1 - 0)) CY CY v (H + mem3 - 0.bit) CY CY v (fmem.bit) CY CY v (pmem7 - 2 + L3 - 2.bit(L1 - 0)) CY CY v (H + mem3 - 0.bit)
CLR1
mem.bit fmem.bit pmem.@L @H + mem.bit
SKT
mem.bit fmem.bit pmem.@L @H + mem.bit
SKF
mem.bit fmem.bit pmem.@L @H + mem.bit
SKTCLR
fmem.bit pmem.@L @H + mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H + mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H + mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H + mem.bit
24
PD75P4308
No. of Machine bytes cycle -- -- Addressing Skip condition area *6
Group Branch
Mnemonic BRNote1
Operand addr
Operation PC12 - 0 addr Assembler selects the most appropriate instruction among the following: * BR !addr * BRCB !caddr * BR $addr PC12 - 0 addr1 Assembler selects the most appropriate instruction among the following: * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC12 - 0 addr PC12 - 0 addr PC12 - 0 addr1 PC12 - 0 PC12 - 8 + DE PC12 - 0 PC12 - 8 + XA PC12 - 0 BCDENote 2 PC12 - 0 BCXA PC12 - 0 addr1 PC12 - 0 PC12 + caddr11 - 0
Note 2
addr1
--
--
*11
!addr $addr $addr1 PCDE PCXA BCDE BCXA BRA
Note 1
3 1 1 2 2 2 2 3 2
3 2 2 3 3 3 3 3 2
*6 *7
*6 *6 *11 *8
!addr1 !caddr
BRCB
Notes 1. Shaded areas indicate support for the Mk II mode only. 2. Only the lower 2 bit in the B register is valid.
25
PD75P4308
No. of Machine bytes cycle 3 3 Addressing Skip condition area *11
Group
Mnemonic
Operand !addr1
Operation (SP - 5) 0, 0, 0, PC12 (SP - 6) (SP - 3) (SP - 4) PC11 - 0 (SP - 2) x, x, MBE, RBE PC12 - 0 addr1, SP SP - 6 (SP -4) (SP - 1) (SP - 2) PC11 - 0 (SP - 3) MBE, RBE, 0, PC12 PC12 - 0 addr, SP SP - 4 (SP - 5) 0, 0, 0, PC12 (SP - 6) (SP - 3) (SP - 4) PC11 - 0 (SP - 2) x, x, MBE, RBE PC12 - 0 addr, SP SP - 6 (SP - 4) (SP - 1) (SP - 2) PC11 - 0 (SP - 3) MBE, RBE, 0, PC12 PC12 - 0 00 + faddr, SP SP - 4 (SP - 5) 0, 0, 0, PC12 (SP - 6) (SP - 3) (SP - 4) PC11 - 0 (SP - 2) x, x, MBE, RBE PC12 - 0 00 + faddr, SP SP - 6 MBE, RBE, 0, PC12 (SP + 1) PC11 - 0 (SP) (SP + 3) (SP + 2) SP SP + 4 x, x, MBE, RBE (SP + 4) 0, 0, 0, PC12 (SP + 1) PC11 - 0 (SP) (SP + 3) (SP + 2) SP SP + 6
Subroutine CALLANote stack control
CALL Note
!addr
3
3
*6
4
CALLFNote
!faddr
2
2
*9
3
RETNote
1
3
RETSNote
1
3+S
MBE, RBE, 0, PC12 (SP + 1) PC11 - 0 (SP) (SP + 3) (SP + 2) SP SP + 4 then skip unconditionally x, x, MBE, RBE (SP + 4) 0, 0, 0, PC12 (SP + 1) PC11, 0 (SP) (SP + 3) (SP + 2) SP SP + 6 then skip unconditionally
Unconditional
RETI
1
3
MBE, RBE, 0, PC12 (SP + 1) PC11 - 0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP + 6 0, 0, 0, PC12 (SP + 1) PC11 - 0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP + 6
Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
26
PD75P4308
No. of Machine bytes cycle 1 2 1 2 2 IExxx DI IExxx I/O IN
Note 1
Group Subroutine stack control
Mnemonic PUSH rp BS POP rp BS
Operand
Operation (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn (n = 0 - 3, 5 - 8) (n = 6)
Addressing Skip condition area
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Interrupt control
EI
2 2 2 2 2 2 2 2 2 1
A, PORTn XA, PORTn
XA PORTn + 1, PORTn PORTn A PORTn +
1,
OUT
Note 1
PORTn, A PORTn, XA
(n = 2 - 3, 5 - 8) (n = 6)
PORTn XA
CPU control
HALT STOP NOP
Set HALT Mode(PCC.2 1) Set STOP Mode(PCC.3 1) No Operation RBS n MBS n (n = 0 - 3) (n = 0, 15) *10
Special
SEL
RBn MBn
2 2 1
GETI
Note 2, 3
taddr
* When using TBR instruction PC12 - 0 (taddr)4 - 0 + (taddr + 1) * When using TCALL instruction (SP - 4) (SP - 1) (SP - 2) PC11 - 0 (SP - 3) MBE, RBE, 0, PC12 PC12 - 0 (taddr) 4 - 0 + (taddr + 1) SP SP - 4 * When using instruction other than TBR or TCALL Execute (taddr) (taddr + 1) instructions
Determined by referenced instruction *10
1
* When using TBR instruction PC12 - 0 (taddr)4 - 0 + (taddr + 1) 4 * When using TCALL instruction (SP - 5) 0, 0, 0, PC12 (SP - 6) (SP - 3) (SP - 4) PC11 - 0 (SP - 2) x, x, MBE, RBE PC12 - 0 (taddr)4 - 0 + (taddr + 1) SP SP - 6 * When using instruction other than TBR or TCALL Execute (taddr) (taddr + 1) instructions
3
Determined by referenced instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL are assembler pseudo-instructions for the GETI instruction's table definitions. 3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
27
PD75P4308
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory in the PD75P4308 is a 8192 x 8-bit electrically write-enabled one-time PROM. The pins listed in the table below are used for this one-time PROM's write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses.
Pin name VPP Function Pin (usually VDD) where programming voltage is applied during program memory write/verify Clock input pin for address updating during program memory write/ verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify
X1, X2
MD0-MD3
D0/P60/KR0-D3/P63/KR3 (lower 4) 8-bit data I/O pin for program memory write/verify D4/P50-D7/P53 (upper 4) VDD Pin where power supply voltage is applied. Power voltage range for normal operation is 1.8 to 5.5 V. Apply 6.0 V for program memory write/verify.
Caution Pins not used for program memory write/verify connect to Vss via a pull-down resistor. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the PD75P4308's VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Operation mode Zero-clear program memory address Write mode Verify mode Program inhibit mode
x : L or H
28
PD75P4308
8.2 Program Memory Write Procedure High-speed program memory write can be executed via the following steps. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down unused pins to VSS via resistors. Set the X1 pin to low. Apply +5 V to the VDD and VPP pins. Wait 10 s. Zero-clear mode for program memory addresses. Apply +6 V to VDD and +12.5 V to VPP. Write data using 1-ms write mode. Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7). X [= number of write operations from steps (6) and (7)] x 1 ms additional write 4 pulse inputs to the X1 pin updates (increments +1) the program memory address.
(10) Repeat steps (6) to (9) until the last address is completed. (11) Zero-clear mode for program memory addresses. (12) Apply +5 V to the VDD and VPP pins. (13) Power supply OFF The following diagram illustrates steps (2) to (9).
X repetitions Write Verify Additional write Address increment
VPP VPP VDD
VDD + 1 VDD VDD
X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53
Data input
Data output
Data input
MD0/P30
MD1/P31
MD2/P32
MD3/P33
29
PD75P4308
8.3 Program Memory Read Procedure The PD75P4308 can read out the program memory contents via the following steps. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down unused pins to VSS via resistors. Set the X1 pin to low. Apply +5 V to the VDD and VPP pins. Wait 10 s. Zero-clear mode for program memory addresses. Apply +6 V to VDD and +12.5 V to VPP. Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. Zero-clear mode for program memory addresses. Apply +5 V to the VDD and VPP pins. Power supply OFF
The following diagram illustrates steps (2) to (7).
VPP VPP VDD
VDD + 1 VDD VDD
X1
D0/P60/KR0D3/P63/KR3 D4/P50D7/P53
Data output
Data output
MD0/P30
MD1/P31
"L"
MD2/P32
MD3/P33
30
PD75P4308
8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high-temperature conditions shown below, the PROM should be verified.
Storage temperature 125C Storage time 24 hours
31
PD75P4308
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage PROM supply voltage Input voltage Symbol VDD VPP VI1 VI2 Output voltage High-level output current VO IOH Per pin Total for all pins Low-level output current IOL Per pin Total for all pins Operating ambient temperature Storage temperature TA Other than port 5 Port 5 (N-ch open-drain) Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD +0.3 -0.3 to +14 -0.3 to VDD +0.3 -10 -30 30 220 -40 to +85 Unit V V V V V mA mA mA mA C
Tstg
-65 to +150
C
Caution If the absolute maximum ratings of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product. Capacitance (TA = 25C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
32
PD75P4308
System Clock Oscillation Circuit Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5. V)
Recommended constants
Resonator Ceramic resonator
Parameter Oscillation frequency (fX)Note 1
Conditions
MIN. 1.0
TYP.
MAX. 6.0Note 3
Unit MHz
X1
X2
Oscillation stabilization timeNote 2 After VDD has reached MIN. value of oscillation voltage range 1.0 4 ms
C1
C2
Crystal resonator
Oscillation frequency (fX)Note 1
6.0Note 3
MHz
X1
X2
Oscillation stabilization timeNote 2 VDD = 5.0 V 10 % 10 ms
C1
C2
30
ms
External clock
X1 X2
X1 input frequency (fX)Note 1
1.0
6.0Note 3
MHz
X1 input high-, low-level widths (tXH, tXL)
83.3
500
ns
Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. 3. When the oscillation frequency fX satisfies 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not set PCC = 0011 as an instruction execution time. If PCC = 0011 is selected, one machine cycle takes less than 0.95 s, and the MIN. value rating of 0.95 s is not satisfied. Caution When using the system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit.
33
PD75P4308
Recommended Oscillation Circuit Constant Ceramic Resonator (TA = -40 to +85C)
Recommended Oscillation voltage Frequency circuit constant (pF) range (VDD) (MHz) C1 C2 MIN. MAX. 1.0 2.0 100 30 -- 3.58 30 -- 30 -- 4.0 30 -- 30 -- 4.19 30 -- 30 -- 6.0 30 -- 30 -- 1.0 2.0 4.0 100 47 33 -- 33 -- 4.19 33 100 30 -- 30 -- 30 -- 30 -- 30 -- 30 -- 30 -- 30 -- 30 -- 100 47 33 -- 33 -- 33 1.8 5.5 1.8 2.4 1.8 5.5 5.5 5.5 On-chip capacitor, TA = -20 to +80C TA = -20 to +80C On-chip capacitor, TA = -20 to +80C TA = -20 to +80C 2.0 On-chip capacitor TA = -20 to +80C 2.9 5.5 On-chip capacitor 1.8 On-chip capacitor 1.9 5.5 On-chip capacitor 1.8 On-chip capacitor 2.0 5.5 On-chip capacitor 1.8 On-chip capacitor 1.8 5.5 On-chip capacitor 2.6 1.8 5.5 5.5 On-chip capacitor Rd = 5.6 k
Manufacturer Murata Manufacturing Co., Ltd.
Product name CSB1000JNote CSA2.00MG CST2.00MG CSA3.58MG CST3.58MGW CSA3.58MGU CST3.58MGWU CSA4.00MG CST4.00MGW CSA4.00MGU CST4.00MGWU CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU
Remark
Kyocera Corp.
KBR-1000F/Y KBR-2.0MS KBR-4.0MSA KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-4.19MSA KBR-4.19MSB KBR-4.19MKS PBRC4.19A PBRC4.19B KBR-6.0MSA KBR-6.0MSB KBR-6.0MKS PBRC6.00A PBRC6.00B
-- 33 -- 6.0 33
-- 33 -- 33 1.8 5.5
On-chip capacitor, TA = -20 to +80C TA = -20 to +80C On-chip capacitor, TA = -20 to +80C TA = -20 to +80C
-- 33 --
-- 33 --
On-chip capacitor, TA = -20 to +80C TA = -20 to +80C On-chip capacitor, TA = -20 to +80C
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used.
34
PD75P4308
Note When using a CSB1000J (1.0 MHz) of Murata Manufacturing Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 5.6 k) is necessary (See diagram below). When using any other recommended resistor, it is not necessary.
X1 CSB1000J C1 X2 Rd C2
35
PD75P4308
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, RESET VIH1 Symbol IOL Per pin Total for all pins Ports 2, 3, 8 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIH3 Port 5 (N-ch open-drain) VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, RESET VIL1 X1 Ports 2, 3, 5, 8 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIL3 High-level output voltage Low-level output voltage VOH X1 SCK, SO, Ports 2, 3, 6 to 8 IOH = -1 mA 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD-0.1 0 0 0 0 0 VDD-0.5 Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V
VOL1
SCK, SO, Ports 2, 3, 5 to 8
IOL = 15 mA, VDD = 5.0 V 10 % IOL = 1.6 mA
0.2
2.0
V
0.4 0.2 VDD
V V
VOL2
SB0
N-ch open-drain Pull-up resistor 1 k Pins other than port 5 and X1 X1
High-level input leakage current
ILIH1 ILIH2 ILIH3
VI = VDD
3 20 20 -3 -20 -3
A A A A A A
VI = 13 V VI = 0 V
Port 5 (N-ch open-drain) Pins other than port 5 and X1 X1 Port 5 (N-ch open-drain) Other than the input instruction execution time Port 5 (N-ch open-drain) At the input instruction execution time
Low-level input leakage current
ILIL1 ILIL2 ILIL3
-30 VDD = 5.0 V VDD = 3.0 V -10 -3 -27 -8
A A A
36
PD75P4308
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter High-level output leakage current Low-level output leakage current On-chip pull-up resistor Supply current Note 1 Symbol ILOH1 ILOH2 ILOL VO = VDD VO = 13 V VO = 0 V Conditions SCK, SO/SB0, Ports 2, 3, 6 to 8 Port 5 (N-ch open-drain) MIN. TYP. MAX. 3 20 -3 Unit
A A A
k
RL
VI = 0 V
Ports 0 to 3, 6 to 8 (except P00 pin) VDD = 5.0 V 10 %Note 2 VDD = 3.0 V 10 %Note 3 HALT mode VDD = 5.0 V 10 % VDD = 3.0 V 10 %
Note 2
50
100
200
IDD1
IDD2
6.0 MHz crystal oscillation C1 = C2 = 22 pF 4.19 MHz crystal oscillation C1 = C2 = 22 pF STOP mode
2.20 0.43 0.53 0.21 1.70 0.35 0.51 0.19 0.05 0.02
7.00 1.30 1.60 0.70 5.10 1.10 1.60 0.60 10.0 5.00 3.00
mA mA mA mA mA mA mA mA
IDD1
VDD = 5.0 V 10 % VDD = 3.0 V 10 % HALT mode
Note 3
IDD2
VDD = 5.0 V 10 % VDD = 3.0 V 10 %
IDD5
VDD = 5.0 V 10 % VDD = 3.0 V 10 % TA = 25C
A A A
0.02
Notes 1. The current flowing through the on-chip pull-up resistor is not included. 2. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 3. When the device operates in low-speed mode with PCC set to 0000.
37
PD75P4308
AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter CPU clock cycle time Note 1 (minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency tCY Symbol Conditions Operates with system clock fTI VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V MIN. 0.67 0.95 0 0 TI0, TI1 input high-, low-level widths Interrupt input high-, low-level widths tINTH, tINTL INT0 IM02 = 0 IM02 = 1 INT1, 2, 4 KR0-7 RESET low-level width tRSL tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 Note 2 10 10 10 10 TYP. MAX. 64 64 1 275 Unit
s s
MHz kHz
s s s s s s
Notes 1. The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY charactersystem clock. 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
Cycle time tCY [ s]
6 5 64 60
tCY vs VDD (with system clock)
istics when the device operates with the
Operation guaranteed range 4 3
2
1
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
38
PD75P4308
Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL1, tKH1
VDD = 2.7 to 5.5 V
tKCY1/2-50 tKCY1/2-150
setup time (to SCK )
tSIK1
VDD = 2.7 to 5.5 V
150 500
SI
Note 1
hold time (from SCK ) tKSI1
VDD = 2.7 to 5.5 V
400 600
SCK SO delay time
Note 1
output
tKSO1
RL = 1 k, CL = 100 pFNote 2
VDD = 2.7 to 5.5 V
0 0
250 1000
ns ns
Notes 1. In the 2-wire serial I/O mode, read SB0 instead. 2. RL and CL are the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL2, tKH2
VDD = 2.7 to 5.5 V
400 1600
setup time (to SCK )
tSIK2
VDD = 2.7 to 5.5 V
100 150
SI
Note 1
hold time (from SCK ) tKSI2
VDD = 2.7 to 5.5 V
400 600
SCK SONote 1 output delay time
tKSO2
RL = 1 k, CL = 100 pFNote 2
VDD = 2.7 to 5.5 V
0 0
300 1000
ns ns
Notes 1. In the 2-wire serial I/O mode, read SB0 instead. 2. RL and CL are the load resistance and load capacitance of the SO output line.
39
PD75P4308
AC timing test points (except X1 input)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock timing
1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V
TI0, TI1 timing
1/fTI tTIL tTIH
TI0, TI1
40
PD75P4308
Serial transfer timing 3-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SI
Input data
tKSO1, 2
SO
Output data
2-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0
tKSO1, 2
41
PD75P4308
Interrupt input timing
tINTL tINTH
INT0, 1, 2, 4 KR0-7
RESET input timing
tRSL
RESET
Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85C)
Parameter Release signal set time Oscillation stabilization wait timeNote 1 Symbol tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 0 215/fx Note 2 TYP. MAX. Unit
s
ms ms
Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
Wait time BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 220/fX 217/fX 215/fX 213/fX fX = 4.19 MHz (approx. 250 ms) (approx. 31.3 ms) (approx. 7.81 ms) (approx. 1.95 ms) 220/fX 217/fX 215/fX 213/fX fX = 6.0 MHz (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms)
42
PD75P4308
Data retention timing (when STOP mode released by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
VDD STOP instruction execution Standby release signal (interrupt request)
VDDDR
tSREL
tWAIT
43
PD75P4308
DC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0V)
Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than X1, X2 X1, X2 Other than X1, X2 X1, X2 VIN = VIL or VIH IOH = - 1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7 VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +13.5 V, including overshoot. 2. Apply VDD before VPP and turn it off after VPP. AC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time (to MD0 )
Note 2
Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR
Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- --
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
MD1 setup time (to MD0 ) Data setup time (to MD0 ) Address hold time (from MD0 )
Note 2
Data hold time (from MD0 ) MD0 data output float delay time VPP setup time (to MD3 ) VDD setup time (to MD3 ) Initial program pulse width Additional program pulse width MD0 setup time (to MD1 ) MD0 data output delay time MD1 hold time (from MD0 ) MD1 recovery time (from MD0 ) Program counter reset time X1 input high-, low-level widths X1 input frequency Initial mode set time MD3 setup time (to MD1 ) MD3 hold time (from MD1 ) MD3 setup time (to MD0 ) Address delay time
Note 2
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read 0 2 2 2 2 130
MHz
s s s s s
ns
data output
AddressNote 2 data output hold time MD3 hold time (from MD0 ) MD3 data output float delay time
s s
Notes 1. 2.
Symbol of corresponding PD27C256A The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not connected to a pin.
44
PD75P4308
Program Memory Write Timing
tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 tI MD0/P30 tPW MD1/P31 tPCR MD2/P32 tM3S MD3/P33 tM3H tM1S tM1H tM1R tM0S tOPW tXL Data input tDS tDH tDV tDF Data output Data input tDS tDH tAH tAS Data input tXH
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 tI MD0/P30 tHAD Data output tDV tM3HR Data output tDFR tDAD tXH
MD1/P31
tPCR MD2/P32 tM3SR MD3/P33
45
PD75P4308
10. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IDD vs VDD (System clock: 6.0 MHz crystal resonator) 10
(TA = 25C)
5.0
PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 System clock HALT mode 0.5
Supply Current IDD (mA)
0.1
0.05
0.01
0.005 X1 X2
Crystal resonator 6.0 MHz
22 pF
22 pF
0.001 0 1 2 3 4 5 Supply Voltage VDD (V) 6 7 8
46
PD75P4308
IDD vs VDD (System clock: 4.19 MHz crystal resonator) 10
(TA = 25C)
5.0
PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000
1.0
System clock HALT mode 0.5
Supply Current IDD (mA)
0.1
0.05
0.01
0.005 X1 X2
Crystal resonator 4.19 MHz
22 pF
22 pF
0.001 0 1 2 3 4 5 Supply Voltage VDD (V) 6 7 8
47
PD75P4308
11. PACKAGE DRAWINGS
36 PIN PLASTIC SHRINK SOP (300 mil)
36
19
detail of lead end
1 A
18
55
H
G
I
J
F
K
E
C D MM
N
B
L
P36GM-80-300B-3 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 15.54 MAX. 0.97 MAX. 0.8 (T.P.)
+0.10 0.35 -0.05
INCHES 0.612 MAX. 0.039 MAX. 0.031 (T.P.) 0.014+0.004 -0.003 0.005 0.003 0.071 MAX. 0.061 0.303 0.012 0.220 0.043 0.008+0.004 -0.002 0.024 -0.009 0.004 0.004
+0.008
0.125 0.075 1.8 MAX. 1.55 7.7 0.3 5.6 1.1 0.20 +0.10 -0.05 0.6 0.2 0.10 0.10
48
PD75P4308
12. RECOMMENDED SOLDERING CONDITIONS
Solder the PD75P4308 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 12-1. Soldering Conditions of Surface Mount Type
PD75P4308GS: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch)
Soldering method
Soldering conditions
Symbol
Infrared reflow
Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125C for 10 hours) Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125C for 10 hours) Solder temperature: 260C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120C or below (package surface temperature) Exposure limit: 7 daysNote (after that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device)
IR35-107-2
VPS
VP15-107-2
Wave soldering
WS60-107-1
Pin partial heating
-
Note The number of days for storage after the dry pack has been opened. Storage conditions are 25C and 65% RH max. Caution Do not use two or more soldering methods in combination (except the pin partial heating method).
49
PD75P4308
APPENDIX A. COMPARISON OF PD750004, 754304, AND 75P4308 FUNCTIONS
(1/2) Item Program memory
PD750004
Mask ROM 0000H-0FFFH (4096 x 8 bits) 000H-1FFH (512 x 4 bits) 75XL CPU
PD754304
Mask ROM 0000H-0FFFH (4096 x 8 bits) 000H-0FFH (256 x 4 bits)
PD75P4308
One-time PROM 0000H-1FFFH (8192 x 8 bits)
Data memory
CPU Instruction execution time When main system clock is selected When subsystem clock is selected I/O ports CMOS input CMOS I/O N-ch open-drain I/O (13-V withstand) Total Timers
* 0.95, 1.91, 3.81, 15.3 s (@ 4.19 MHz) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0 MHz) 122 s (@ 32.768 kHz) No subsystem clock
8 (connections of on-chip pull-up resistors are software-specifiable: 7) 18 (connections of on-chip pull-up resistors are software-specifiable) 8 (on-chip pull-up resistors 4 (on-chip pull-up resistors 4 (No mask option) are specified by mask option) are specified by mask option) 34 4 channels * Basic interval timer/ watchdog timer * 8-bit timer/event counter * 8-bit timer * Watch timer 30 (No port 4 pin) 3 channels * Basic interval timer/watchdog timer * 8-bit timer/event counter 0 (fx/22 added) * 8-bit timer/event counter 1 (TI1, fx/22 added) (Can be used as a 16-bit timer/event counter)
Clock output (PCL)
* , 524, 262, 65.5 kHz (main system clock: @ 4.19 MHz) * , 750, 375, 93.8 kHz (main system clock: @ 6.0 MHz) Yes Can support three modes * 3-wire serial I/O mode ...MSB/LSB-first switchable * 2-wire serial I/O mode * SBI mode Yes No Can support two modes * 3-wire serial I/O mode...MSB/LSB-first switchable * 2-wire serial I/O mode
BUZ output Serial interface
Watch mode register (WM) System clock control register (SCC) Sub-oscillator control register (SOS)
No
50
PD75P4308
(2/2) Item Memory bank select register (MBS) Stack bank select register (SBS) Timer/event counter mode register (TM0, TM1) Vectored interrupts Test inputs Test enable flag (IEW) Test request flag (IRQW) Power supply voltage Operating ambient temperature Package VDD = 2.2 to 5.5 V TA = -40 to +85C * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm) * 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) VDD = 1.8 to 5.5 V
PD750004
Selectable from memory banks 0 and 1 Bits 0, 1, and 7 are fixed at 0
PD754304
Fixed at memory bank 0
PD75P4308
-
External: 3, Internal: 4 External: 1, Internal: 1 Yes External: 1 No
51
PD75P4308
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are provided for system development using the PD75P4308. In the 75XL series, the common relocatable assembler is used together with the device file of each model.
RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOSTM Ver.3.30 to Ver.6.2Note IBM PC/ATTM or compatible Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD Part No. (name)
S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
3.5" 2HC 5" 2HC
Device file
Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD Part No. (name)
S5A13DF754304 S5A10DF754304 S7B13DF754304 S7B10DF754304
3.5" 2HC 5" 2HC
Note Ver. 5.00 and above include a task swapping function, but this software is not able to use that function. Remark Operations of the assembler and the device file are guaranteed only when using the host machine and OS described above.
52
PD75P4308
PROM Write Tools
Hardware PG-1500 A stand-alone system can be configured of a single-chip microcontroller with on-chip PROM when connected to an auxiliary board (attached) and a programmer adapter (separately sold). Alternatively, a PROM programmer can be operated on a host machine for programming. In addition, typical PROMs in capacities ranging from 256 K to 4 Mbits can be programmed. This is a PROM programmer adapter for the PD75P4308GS. It can be used when connected to a PG-1500. Establishes serial and parallel connections between the PG-1500 and a host machine for hostmachine control of the PG-1500. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD Part No. (name)
PA-75P4308GS
Software
PG-1500 controller
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
3.5" 2HD 5" 2HC
Note Ver. 5.00 and above include a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
53
PD75P4308
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P4308. Various system configurations using these in-circuit emulators are listed below.
Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. For development of the PD754304 subseries, the IE-75000-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe (EP-754304GS-R). These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe (EP-754304GS-R). These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. This is an emulation board for evaluating application systems that use the PD754304 subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator. This is an emulation probe for the PD75P4308. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a flexible board (EV-9500GS-36) to facilitate connections with various target systems. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note 2 IBM PC/AT or compatible Refer to OS for IBM PCs 3.5" 2HC 5" 2HC Supply medium 3.5" 2HD 5" 2HD Part No. (name)
IE-75001-R
IE-75300-R-EM
EP-754304GS-R EV-9500GS-36
Software
IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. This is a service part provided for maintenance purpose only. 2. Ver. 5.00 and above include a task swapping function, but this software is not able to use that function. Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described above. 2. The PD754302, 754304, and 75P4308 are commonly referred to as the PD754304 subseries.
54
PD75P4308
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS PC DOS
TM
Version Ver.5.02 to Ver.6.3 J6.1/V to J6.3/V Ver.5.0 to Ver.6.22 5.0/V to 6.2/V J5.02/V
MS-DOS
IBM DOSTM
Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.
55
PD75P4308
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Device
Document Number Document Name Japanese U10797J U10909J English U10797E U10909E (this document) U10123E -- U10453E
PD754302, 754304 Data Sheet PD75P4308 Data Sheet PD754304 User's Manual PD754304 Instruction Table
75XL Series Selection Guide
U10123J IEM-5605 U10453J
Documents Related to Development Tools
Document Number Document Name Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-754304GS-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language PC9800 Series (MS-DOS) base IBM PC/AT Series (PC DOS) base Japanese EEU-846 U11354J U10677J EEU-651 EEU-731 EEU-730 EEU-704 EEU-5008 English EEU-1416 U11354E U10677E EEU-1335 EEU-1346 EEU-1363 EEU-1291 U10540E
Other Related Documents
Document Number Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer-Related Product Guide -Third Party Products- Japanese C10943X C10535J C11531J C10983J MEM-539 MEI-603 U11416J C10535E C11531E C10983E -- MEI-1202 -- English
Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc.
56
PD75P4308
[MEMO]
57
PD75P4308
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
58
PD75P4308
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
59
PD75P4308
MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

▲Up To Search▲

Price & Availability of UPD75P4308

	To Download UPD75P4308 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .